1. Field
The present application relates generally to the operation and design of power amplifiers, and more particularly, to the operation and design of electrostatic discharge protection for power amplifier integrated circuits.
2. Background
A Class D Power Amplifier (PA) integrated circuit (IC) can be used in a device to drive an off-chip audio speaker. Typically, such a device needs to provide electrostatic discharge (ESD) protection in accordance with industry standards, such as standards developed by the International Electrotechnical Commission (IEC). One such standard, referred to as “IEC 61000-4-2” requires system level protection of 8KV contact and 15KV air discharge. This standard requires a system to have the capability to sink close to 20 amps of peak current during an IEC ESD event. In contrast, a less rigorous standard, referred to “Human Body Model” (HBM) requires only 2KV of protection which translates to 1.3 amps of peak currents. The HBM is a standard for component level ESD testing while IEC 61000-4-2 is a standard for system level ESD testing. A Class D PA used in real applications needs to satisfy both HBM and IEC standards.
In one implementation, the Class D PA IC may provide two interface pins that are used to output audio signals and two interface pins that are used to receive voltage sensing signals. Thus, the Class D PA IC may have four or more interface pins that require ESD protection for both HBM and IEC discharge events.
Typically, external transient voltage suppression (TVS) diodes are used to provide ESD protection for integrated circuits. However, TVS diodes are expensive and may lead to excessive bill of material (BOM) costs depending on the number of IC interface pins that require ESD protection.
Accordingly, it would be desirable to have a simple and low cost mechanism to provide ESD protection for interface pins of a Class D PA against HBM and IEC discharge events.